1. Field of the Invention
The present invention relates to memory circuits and, and, in particular, to error correction in flash memory devices.
2. Description of the Related Art
High-density flash memories, such as USB-port mass-storage flash devices, SD cards, XD cards, and compact flash cards, generally use advanced error protection/correction data processing, such as BCH (Bose, Ray-Chaudhuri, Hocquenhem) and Reed-Soloman error correcting codes, to correct for defective or erroneous bits read from within the flash memory. High-density flash memory is typically limited to a maximum capacity of about 8 Gbytes. Evolution of high-density flash technology leads to more memory cells per chip, memory cells that store more than 2 binary bits of information, and more-sophisticated error correction techniques.
A single-level memory storage cell (SLC) contains a single binary bit of information represented as one of two levels of stored charge. When data is read from flash memory, the amount of charge stored within the flash memory cell is detected by sense amplifiers. Sense amplifiers usually generate digital output values based on the detected charge level, but some sense amplifiers might generate analog output values. FIG. 1A shows SLC flash memory 100 of the prior art having memory array 101 and sense amplifier unit 102. SLC flash memory 100 generates digital output values when addressed and read. Memory array 101 comprises SLC flash cells 103 addressed by particular row drivers (not shown in the figure). Sense amplifier unit 102 includes i) sense amplifiers 104 that sense the charge stored in a particular SLC, and ii) column decoder 105 (or digital multiplexer) that provides a particular binary bit value based on the output of a corresponding one of sense amplifiers 104 and a unique column address.
Flash memory has evolved from an SLC that contains a single binary bit (2-levels of charge store) to a multi-level cell (MLC) that contains a plurality of bits of information. Currently, the common implementation for an MLC contains 2 binary bits of information, each bit-pair represented as one of four available discrete charge levels stored within the cell.
A number of techniques exist for detecting the data state of an MLC. For an MLC capable of storing two bits of data in one of four discrete levels, one technique is to use multiple sense amplifiers, each capable of discriminating between two of the four possible charge levels within the cell. Instead of having a single sense amplifier associated with each column, as with the SLC flash memory shown in FIG. 1A, several sense amplifiers are associated with each column of the MLC flash memory, as illustrated in prior art MLC flash memory 110 of FIG. 1B.
MLC flash memory 110 comprises MLC flash cells 113 of MLC memory array 111, and sense amplifier unit 112 having multiple sense amplifiers (MSAs) 114, and column decoder 115. Table 1 shows two exemplary methods of using three sense amplifiers for an MSA to generate, when decoded by column decoder 115, an output 2-bit data code (00, 01, 10, 11) by logical combination of the sense amplifier output levels in the MSA.
TABLE 1ExampleSense AmplifierCharge Levels Discriminated11Between Level 1 and Level 22Between Level 1 and Level 33Between Level 1 and Level 421Between Levels 1 + 2 and Levels 3 + 42Between Level 1 and Level 23Between Level 3 and Level 4
Another technique for MLC flash memory is the use of one sense amplifier which, in temporal sequence, discriminates between the three various pairs of levels (sequential sense amplifiers). Using sequential sense amplifiers generally results in smaller area on, for example, an integrated circuit (IC) implementation, than the multiple sense amplifier approach. However, because sensing is iterative, using sequential sense amplifiers takes a longer period of time for level detection. A prior art sequential sense amplifier MLC flash memory 120 is shown in FIG. 1C. Sequential sense amplifier MLC flash memory 120 includes MLC memory cell array 121 with MLCs 123, and sense amplifier unit 122 having sequential sense amplifiers (SSAs) 124, column decoder 125, and control logic 126. SSAs 124 are designed for sequential discriminations of different charge levels within the MLCs 123, and control logic 126 controls temporal sequencing of the sense amplifiers.
Flash memory cells store data by storing charge within the flash cell as follows. During write operations, electrons are either injected into or withdrawn from the charge storage structure within the cell. The cell is primarily implemented with a MOSFET (metal-oxide-semiconductor field-effect transistor) transistor that has a threshold voltage proportional to the charge stored. If the MOSFET is an N-channel transistor, the larger the amount of negative charge stored, the higher the threshold voltage. If the MOSFET is a P-channel transistor, the larger the amount of negative charge stored, the lower the threshold voltage. In an MLC cell, there are 2N charge storage levels (CSLs), where N is the number of bits stored within the cell (e.g., if N=2, the CSL=4, and if N=4, the CSL=16). Two common types of charge storage structures within flash cells are in commercial production. The most common is the floating poly-silicon gate structure. Charge is stored on a conductive poly-silicon gate that is entirely surrounded by dielectric material. The less common charge storage structure is an oxide-nitride-oxide (ONO) gate dielectric structure in which charge is retained within the non-conductive dielectric structure.
In either case, the dielectric surrounding the charge storage structures, ideally, might prevent the charge from ever leaking off, or charge ever leaking onto, the charge storage structure. However, in practice, charge leaks at a rate that is dependent upon the physical and electrical characteristics of the structure. To have a good-quality flash memory cell, the rate of charge loss or gain should be very low (e.g., measurable in terms of years). The term “charge drift” is employed herein to mean charge leaking off of or onto the charge storage structure of the cell. The cell threshold voltage slowly drifts up or down as charge leaks off of or onto the charge storage structure, and the term “threshold drift” is employed herein to indicate this change in threshold voltage associated with the charge drift.